NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 165

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.13.4.1
5.13.4.2
5.13.5
Intel
®
ICH8 Family Datasheet
PCI Express* SCI
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, ICH8 will set the PCI_EXP_STS bit. If the
PCI_EXP_EN bit is also set, the ICH8 can cause an SCI via the GPE1_STS register.
PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1
register. It is also capable of generating an SMI. However, it is not capable of
generating a wake event.
Dynamic Processor Clock Control
The ICH8 has extensive control for dynamically starting and stopping system clocks.
The clock control is used for transitions among the various S0/Cx states, and processor
throttling. Each dynamic clock control method is described in this section. The various
sleep states may also perform types of non-dynamic clock control.
The ICH8 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3, and C4
(in mobile) states.
The Dynamic Processor Clock control is handled using the following signals:
The C1 state is entered based on the processor performing an auto halt instruction.
(Mobile Only) The C2 state is entered based on the processor reading the Level 2
register in the ICH8. It can also be entered from C3 or C4 states if bus masters require
snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set.
(Mobile Only) The C3 state is entered based on the processor reading the Level 3
register in the ICH8 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit 7).
This state can also be entered after a temporary return to C2 from a prior C3 or C4
state.
(Mobile Only) The C4 state is entered based on the processor reading the Level 4
register in the ICH8, or by reading the Level 3 register when the C4onC3_EN bit is set.
This state can also be entered after a temporary return to C2 from a prior C4 state.
A C1 state in desktop or a C1, C2, C3 or C4 state in mobile ends due to a Break event.
Based on the break event, the ICH8 returns the system to C0 state.
(Mobile Only)
events from C1 are indicated in the processor’s datasheet.
• STPCLK#: Used to halt processor instruction stream.
• (Mobile Only) STP_CPU#: Used to stop processor’s clock
• (Mobile Only) CPUSLP#: Asserted prior to STP_CPU# (in stop grant mode)
• (Mobile Only) DPSLP#: Used to force Deeper Sleep for processor.
• (Mobile Only) DPRSLPVR: Used to lower voltage of VRM during C4 state.
• (Mobile Only) DPRSTP#: Used to alert the processor of C4 state. Also works in
conjunction with DPRSLPVR to communicate to the VRM whether a slow or fast
voltage ramp should be used.
Table 66
lists the possible break events from C2, C3, or C4. The break
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