NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 376

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.7.4
9.7.5
376
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
RST_CNT—Reset Control Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bits
7:0
7:4
Bit
3
2
1
0
Coprocessor Error (COPROC_ERR) — WO. Any value written to this register will
cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to
generate an internal IRQ13, the COPROC_ERR_EN bit (Chipset Configuration Register,
Offset 31FFh, bit 1) must be 1.
Reserved
Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#,
SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),
after PWROK going low (with RSMRST# high), or after two TCO timeouts.
0 = ICH8 will keep SLP_S3#, SLP_S4# and SLP_S5# high.
1 = ICH8 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)
Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a
hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to
the processor.
0 = When RST_CPU bit goes from 0 to 1, the ICH8 performs a soft reset by activating
1 = When RST_CPU bit goes from 0 to 1, the ICH8 performs a hard reset by activating
Reserved
INIT# for 16 PCI clocks.
PLTRST# and SUS_STAT# active for about 5-6 milliseconds. In this case,
SLP_S#3, SLP_S4#, and SLP_S5# state (assertion or de-assertion) depends on
FULL_RST bit setting. The ICH8 main power well is reset when this bit is 1. It also
resets the resume well bits (except for those noted throughout the datasheet).
in response to SYSRESET#, PWROK#, and Watchdog timer reset sources.
F0h
00h
No
CF9h
00h
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
WO
8-bits
Core
R/W
8-bit
Core
Intel
®
ICH8 Family Datasheet