NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 233

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.20.7.1
Note:
Table 92.
Intel
®
ICH8 Family Datasheet
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH8 SMBus Slave I/F. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field
(bits 20:27) indicate the value that should be written to that register.
If the ICH8 is sent a ‘Hard Reset Without Cycling’ command on SMBus while the system
is in S4 or S5, the reset command and any other write commands accepted by the
ICH8 SMBus will not be executed until the next wake event. SMBus write commands
that are accepted by the ICH8 are not lost, but completion occurs after the next system
wake event. This also applies to any SMBus wake commands accepted after a ‘Hard
Reset Without Cycling’ command, such that the SMBus wake command will not cause
the system to wake. Any SMBus read that is accepted by the ICH8 will complete
normally. Intel® Active Management Technology is not impacted as Intel AMT does not
use the Hard Reset Without Cycling command while the system is in S4 or S5.
Table 92
Slave Write Registers
NOTE: The external microcontroller is responsible to make sure that it does not update the
Register
9–FFh
1–3
6–7
contents of the data byte registers until they have been read by the system processor. The
ICH8 overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read. ICH8
will not attempt to cover this race condition
(i.e., unpredictable results in this case).
0
4
5
8
has the values associated with the registers.
Command Register. See
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Reserved
Reserved
Table 93
below for valid values written to this register.
Function
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