NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 262

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 102.
262
Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
NOTES:
1.
2.
512 B anywhere in 64-bit
addressing space
FED0 X000h–FED0 X3FFh
FFB0 0000h–FFB7 FFFFh
FFB8 0000h–FFBF FFFFh
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
FFF0 0000h–FFF7 FFFFh
FFF8 0000h–FFFF FFFFh
1 KB anywhere in 4-GB
1 KB anywhere in 4-GB
128 KB anywhere in 4-
Memory Range
Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High
Precision Event Timers. If attempted, the lock is not honored, which means potential
deadlock conditions may occur.
PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Config
Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits
have no effect.
GB range
All other
range
range
USB EHCI Controller #1
USB EHCI Controller #2
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Intel
Audio Host Controller
High Precision Event
Integrated LAN
®
Controller
Timers
High Definition
Target
PCI
1
3
2
2
2
2
2
2
1
1
Bit 13 in Firmware Hub Decode Enable
register is set
Bit 14 in Firmware Hub Decode Enable
register is set
Always enabled.
The top two, 64 KB blocks of this range
can be swapped, as described in
Section
Bit 3 in Firmware Hub Decode Enable
register is set
Bit 2 in Firmware Hub Decode Enable
register is set
Bit 1 in Firmware Hub Decode Enable
register is set
Bit 0 in Firmware Hub Decode Enable
register is set
Enable via BAR in Device 25:Function 0
(Integrated LAN Controller)
Enable via standard PCI mechanism
(Device 29, Function 7)
Enable via standard PCI mechanism
(Device 26, Function 7)
Enable via standard PCI mechanism
(Device 27, Function 0)
BIOS determines the “fixed” location
which is one of four, 1-KB ranges where X
(in the first column) is 0h, 1h, 2h, or 3h.
None
Dependency/Comments
7.4.1.
Register and Memory Mapping
Intel
®
ICH8 Family Datasheet