NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 206

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.18
5.18.1
5.18.2
5.18.3
5.18.4
5.18.4.1
5.18.4.2
5.18.4.3
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USB UHCI Host Controllers (D29:F0, F1, F2 and
D26:F0, F1)
The ICH8 contains five USB full/low-speed host controllers that support the standard
Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller
(UHC) includes a root hub with two separate USB ports each, for a total of ten USB
ports.
Data Structures in Main Memory
Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1
details the data structures used to communicate control, status, and data between
software and the ICH8.
Data Transfers to/from Main Memory
Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1
describes the details on how HCD and the ICH8 communicate via the Schedule data
structures.
Data Encoding and Bit Stuffing
The ICH8 USB employs NRZI data encoding (Non-Return to Zero Inverted) when
transmitting packets. Full details on this implementation are given in the Universal
Serial Bus Specification, Revision 2.0.
Bus Protocol
Bit Ordering
Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb,
through to the most significant bit (MSb) last.
SYNC Field
All packets begin with a synchronization (SYNC) field, which is a coded sequence that
generates a maximum edge transition density. The SYNC field appears on the bus as
IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the
input circuitry to align incoming data with the local clock and is defined to be 8 bits in
length. SYNC serves only as a synchronization mechanism. Full details are given in the
Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1. The last two bits in
the SYNC field are a marker that is used to identify the first bit of the PID. All
subsequent bits in the packet must be indexed from this point.
Packet Field Formats
All packets have distinct start and end of packet delimiters. Full details are given in the
Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1.
• Overcurrent detection on all ten USB ports is supported. The overcurrent inputs are
• The ICH8’s UHCI host controllers are arbitrated differently than standard PCI
• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows
not 5 V tolerant, and can be used as GPIs if not needed.
devices to improve arbitration latency.
support for USB full-speed signaling rates, instead of USB I/O buffers.
Intel
®
Functional Description
ICH8 Family Datasheet