NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 519

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.4.1.7
12.4.1.8
Intel
®
ICH8 Family Datasheet
CCC_Ports—Command Completion Coalescing Ports Register (D31:F2)
Address Offset: ABAR + 18h–1Ch
Default Value:
This register is used to specify the ports that are coalesced as part of the CCC feature
when CCC_CTL.EN = ‘1’. This register is reserved if command coalescing is not
supported (CAP_CCCS = ‘0’).
EM_LOC—Enclosure Management Location Register (D31:F2)
Address Offset: ABAR + 1Ch–1Fh
Default Value:
This register identifies the location and size of the enclosure management message
buffer. This register is reserved if enclosure management is not supported (i.e.
CAP.EMS = 0).
31:16
31:0
15:0
Bit
Bit
Ports (PRT) — R/W.
0 = The port is not part of the command completion coalescing feature.
1 = The corresponding port is part of the command completion coalescing feature.
Bits set to 1 in this register must also have the corresponding bit set to 1 in the Ports Implemented
register. An updated value for this field shall take effect within one timer increment (1 millisecond).
Offset (OFST) — RO. The offset of the message buffer in DWords from the beginning
of the ABAR.
Buffer Size (SZ) — RO. Specifies the size of the transmit message buffer area in
DWords. The ICH8 SATA controller only supports transmit buffer.
A value of 0 is invalid.
Bits set to ‘1’ in this register must also have the corresponding bit set to ‘1’ in the
Ports Implemented register.
00000000h
01000002h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
RO
32 bits
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