NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 127

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.4.1.5
Table 46.
5.4.1.6
5.4.1.7
5.4.1.8
Intel
®
ICH8 Family Datasheet
SYNC
Valid values for the SYNC field are shown in
SYNC Bit Definition
NOTES:
1.
2.
SYNC Time-Out
There are several error cases that can occur on the LPC interface. The ICH8 responds
as defined in Section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1
to the stimuli described therein. There may be other peripheral failure conditions;
however, these are not handled by the ICH8.
SYNC Error Indication
The ICH8 responds as defined in Section 4.2.1.10 of the Low Pin Count Interface
Specification, Revision 1.1.
Upon recognizing the SYNC field indicating an error, the ICH8 treats this as an SERR by
reporting this into the Device 31 Error Reporting Logic.
LFRAME# Usage
The ICH8 follows the usage of LFRAME# as defined in the Low Pin Count Interface
Specification, Revision 1.1.
The ICH8 performs an abort for the following cases (possible failure cases):
• ICH8 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after
• ICH8 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC
• A peripheral drives an invalid address when performing bus master cycles.
• A peripheral drives an invalid value.
Bits[3:0]
four consecutive clocks.
pattern.
0000
0101
0110
1001
1010
All other combinations are RESERVED.
If the LPC controller receives any SYNC returned from the device other than short (0101),
long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may
occur. A FWH device is not allowed to assert an Error SYNC.
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA
request deassertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the Intel
does not use this encoding. Instead, the ICH8 uses the Long Wait encoding (see
next encoding below).
Long Wait: Part indicating wait-states, and many wait-states will be added. This
encoding driven by the ICH8 for bus master cycles, rather than the Short Wait
(0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with
no error and more DMA transfers desired to continue after this transfer. This
value is valid only on DMA transfers and is not allowed for any other type of
cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or
IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred,
but there is a serious error in this transfer. For DMA transfers, this not only
indicates an error, but also indicates DMA request deassertion and no more
transfers desired for that channel.
Table
Indication
46.
®
ICH8
127