NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 402

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.8.3.12
402
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, the ICH8 will generate a Wake Event. Once back in an S0 state (or if already in
an S0 state when the event occurs), the ICH8 will also generate an SCI if the SCI_EN
bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are
reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#.
31:16
Bit
15
14
13
12
GPIOn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and
NOTE: Mapping is as follows: bit 31 corresponds to GPIO[15]... and bit 16
Reserved
USB4_STS — R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
PME_B0_STS — R/WC. This bit will be set to 1 by the ICH8 when any internal
device with PCI Power Management capabilities on bus 0 asserts the equivalent of
the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an
S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if
SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4
state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the
PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not
set) will be generated. If the system is in an S5 state due to power button
override, then the PME_B0_STS bit will not cause a wake event or SCI.
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
Note: On ICH8, HD audio wake events are changed to be reported in this bit.
ME “maskable” wake events are also reported in this bit.
USB3_STS — R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.
the corresponding GPIO signal is high (or low if the corresponding GP_INV bit
is set). If the corresponding enable bit is set in the GPE0_EN register, then
when the GPIO[n]_STS bit is set:
resume well reset. This bit is set when USB UHCI controller #4 needs to cause
a wake. Additionally if the USB4_EN bit is set, the setting of the USB4_STS bit
will generate a wake event.
resume well reset. This bit is set when USB UHCI controller #3 needs to cause
a wake. Additionally if the USB3_EN bit is set, the setting of the USB3_STS bit
will generate a wake event.
PMBASE + 28h
(ACPI GPE0_BLK)
00000000h
No
Resume
corresponds to GPIO[0].
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
R/WC
32-bit
ACPI
Intel
®
ICH8 Family Datasheet