NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 705

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express* Configuration Registers
18.1.13
18.1.14
Intel
®
ICH8 Family Datasheet
SLT—Secondary Latency Timer
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Bh
Default Value:
IOBL—I/O Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Ch–1Dh
Default Value:
15:12
11:8
7:0
7:4
3:0
Bit
Bit
Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base
Specification.
I/O Limit Address (IOLA) — R/W. This field provides I/O Base bits corresponding to
address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support
32-bit I/O addressing.
I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12
for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Base Address Capability (IOBC) — R/O. Indicates that the bridge does not support
32-bit I/O addressing.
0h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W, RO
16 bits
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