NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 709

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express* Configuration Registers
18.1.21
18.1.22
Intel
®
ICH8 Family Datasheet
INTR—Interrupt Information Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 3Ch–3Dh
Default Value:
BCTRL—Bridge Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 3Eh–3Fh
Default Value:
15:12
15:8
7:0
Bit
Bit
11
10
9
8
7
6
5
4
Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the root
port. At reset, this register takes on the following values, which reflect the reset state
of the D28IP register in chipset configuration space:
NOTE: The value that is programmed into D28IP is always reflected in this register.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register.
Reserved
Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification,
Revision 1.0a
Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision
1.0a.
Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification,
Revision 1.0a.
Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision
1.0a.
Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification,
Revision 1.0a.
Secondary Bus Reset (SBR) — R/W. Triggers a hot reset on the PCI Express* port.
Master Abort Mode (MAM): Reserved per Express specification.
VGA 16-Bit Decode (V16) — R/W.
0 = VGA range is enabled.
1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled,
Port
and only the base I/O ranges can be decoded
1
2
3
4
5
6
See bit description
0000h
Reset Value
D28IP.P1IP
D28IP.P2IP
D28IP.P3IP
D28IP.P4IP
D28IP.P5IP
D28IP.P6IP
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, RO
16 bits
R/W
16 bits
709