NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 513

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.4.1
Table 125.
12.4.1.1
Intel
®
ICH8 Family Datasheet
AHCI Generic Host Control Registers (D31:F2)
Generic Host Controller Register Address Map
CAP—Host Capabilities Register (D31:F2)
Address Offset: ABAR + 00h–03h
Default Value:
All bits in this register that are R/WO are reset only by PLTRST#.
0Ch–0Fh
ABAR +
10h-13h
08–0Bh
Offset
00–03
04–07
Bit
31
30
29
28
27
26
25
Mnemonic
Supports 64-bit Addressing (S64A) — RO. Indicates that the SATA controller can
access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the
PRD Base, and each PRD entry are read/write.
Supports Command Queue Acceleration (SCQA) — RO. Hardwired to 1 to
indicate that the SATA controller supports SATA command queuing via the DMA
Setup FIS. The Intel® ICH8 handles DMA Setup FISes natively, and can handle
auto-activate optimization through that FIS.
Supports SNotification Register (SSNTF): — RO. The ICH8 SATA Controller does not
support the SNotification register.
Supports Interlock Switch (SIS) — R/WO. Indicates whether the SATA controller
supports interlock switches on its ports for use in Hot-Plug operations. This value is
loaded by platform BIOS prior to OS initialization.
If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through
GPIO space.
Supports Staggered Spin-up (SSS) — R/WO. Indicates whether the SATA
controller supports staggered spin-up on its ports, for use in balancing power spikes.
This value is loaded by platform BIOS prior to OS initialization.
0 = Staggered spin-up not supported.
1 = Staggered spin-up supported.
Supports Aggressive Link Power Management (SALP) — R/WO.
0 = Software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved.
1 = The SATA controller supports auto-generating link requests to the partial or
Supports Activity LED (SAL) — RO. Indicates that the SATA controller supports a
single output pin (SATALED#) which indicates activity.
GHC
CAP
VS
IS
PI
slumber states when there are no commands to process.
FF22FFC2h (Desktop)
DE127F03h (Mobile)
Host Capabilities
Global ICH8 Control
Interrupt Status
Ports Implemented
AHCI Version
Register
Description
Attribute:
Size:
DE227F03h
DE127F03h
00000000h
00000000h
00000000h
00010100h
(desktop)
(mobile)
Default
R/WO, RO
32 bits
R/WO, RO
R/WO, RO
R/WC, RO
Type
R/W
RO
513