NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 463

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDE Controller Registers (D31:F1) (Mobile Only)
11.2.2
11.2.3
Intel
®
ICH8 Family Datasheet
BMISP—Bus Master IDE Status Register (IDE—D31:F1)
Address Offset:
Default Value:
BMIDP—Bus Master IDE Descriptor Table Pointer Register
(IDE—D31:F1)
Address Offset:
Default Value:
31:2
4:3
1:0
Bit
Bit
7
6
5
2
1
0
PRD Interrupt Status (PRDIS) — R/WC.
0 = When this bit is cleared by software, the interrupt is cleared.
1 = Set when the host controller completes execution of a PRD that has its Interrupt bit (bit 2 of
Drive 1 DMA Capable — R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this
Reserved. Returns 0.
Interrupt — R/WC. Software can use this bit to determine if an IDE device has
asserted its interrupt line (IDEIRQ).
0 = Software clears this bit by writing a 1 to it. If this bit is cleared while the interrupt is still active,
1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when transferring
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH8M when the last transfer for a region is performed, where EOT for
1 = Set by the ICH8M when the Start bit is written to the Command register.
Address of Descriptor Table (ADDR) — R/W. Corresponds to A[31:2]. The
Descriptor Table must be dword-aligned. The Descriptor Table must not cross a 64-K
boundary in memory.
Reserved
this register) set.
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH8M does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH8M does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
this bit will remain clear until another assertion edge is detected on the interrupt line.
masked in the 8259 or the internal I/O APIC. When this bit is read as 1, all data transferred
from the drive is visible in system memory.
data on PCI.
that region is set in the region descriptor. It is also cleared by the ICH8M when the Start bit is
cleared in the Command register. When this bit is read as 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the bus master
command was aborted.
BMIBASE + 02h
00h
BMIBASE + 04h
All bits undefined
Description
Description
§ §
Attribute:
Size:
Attribute:
Size:
R/W, R/WC
8 bits
R/W
32 bits
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