NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 63

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Description
2.6
Table 10.
Intel
®
ICH8 Family Datasheet
PCI Interface
PCI Interface Signals (Sheet 1 of 3)
C/BE[3:0]#
AD[31:0]
DEVSEL#
FRAME#
Name
Type
I/O
I/O
I/O
I/O
PCI Address/Data: AD[31:0] is a multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a
physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The Intel
the address phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/
BE[3:0]# define the Byte Enables.
All command encodings not shown are reserved. The ICH8 does not
decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.
Device Select: The ICH8 asserts DEVSEL# to claim a PCI
transaction. As an output, the ICH8 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH8 address
or an address destined DMI (main memory or graphics). As an
input, DEVSEL# indicates the response to an ICH8-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PLTRST#. DEVSEL# remains tri-stated by the ICH8 until
driven by a target device.
Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator
asserts FRAME#, data transfers continue. When the initiator
negates FRAME#, the transaction is in the final data phase.
FRAME# is an input to the ICH8 when the ICH8 is the target, and
FRAME# is an output from the ICH8 when the ICH8 is the initiator.
FRAME# remains tri-stated by the ICH8 until driven by an initiator.
C/BE[3:0]#
0000b
0001b
0010b
0011b
0110b
0111b
1010b
1011b
1100b
1110b
1111b
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
®
ICH8 will drive all 0s on AD[31:0] during
Description
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