NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 269

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chipset Configuration Registers
7.1.4
7.1.5
7.1.6
Intel
®
ICH8 Family Datasheet
PVC—Port Virtual Channel Control Register
Offset Address: 000C–000Dh
Default Value:
PVS—Port Virtual Channel Status Register
Offset Address: 000E–000Fh
Default Value:
V0CAP—Virtual Channel 0 Resource Capability Register
Offset Address: 0010–0013h
Default Value:
15:04
15:01
31:24
22:16
13:8
3:1
7:0
Bit
Bit
Bit
23
15
14
0
0
Reserved
VC Arbitration Select (AS) — RO. Indicates which VC should be programmed in the
VC arbitration table. The root complex takes no action on the setting of this field
since there is no arbitration table.
Load VC Arbitration Table (LAT) — RO. Indicates that the table programmed should
be loaded into the VC arbitration table. This bit is defined as read/write with always
returning 0 on reads.
Reserved
VC Arbitration Table Status (VAS) — RO. Indicates the coherency status of the VC
Arbitration table when it is being updated. This field is always 0 in the root complex
since there is no VC arbitration table.
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table
since the arbitration is fixed.
Reserved
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and
therefore this field is not used.
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not
just advanced packet switching transactions.
Reserved
Port Arbitration Capability (PAC) — RO. Indicates that this VC uses fixed port
arbitration.
0000h
0000h
00000001h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W, RO
16-bit
RO
16-bit
RO
32-bit
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