NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 791

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thermal Sensor Registers (D31:F6)
21.1.4
21.1.5
21.1.6
Intel
®
ICH8 Family Datasheet
STS—Status
Address Offset: 06h
Default Value:
RID—Revision Identification
Address Offset: 08h
Default Value:
PI— Programming Interface
Address Offset: 09h
Default Value:
10:9
2:0
Bit
7:0
7:0
Bit
Bit
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC. Software clears this bit by writing a 1 to this
bit location.
0 = Parity did Not occur.
1 = Parity error occurs on the internal interface for this function, regardless of the
SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.
Received Master Abort (RMA) — RO. Not implemented. Hardwired to 0.
Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.
Signaled Target-Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEVT) — RO. Does not apply. Hardwired to 0.
Master Data Parity Error (MDPE) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FBC) — RO. Does not apply. Hardwired to 0.
Reserved
66 MHz Capable (C66) — RO. Does not apply. Hardwired to 0.
Capabilities List Exists (CLIST) — RO. This bit indicates that the controller contains
a capabilities pointer list. The first item is pointed to by looking at configuration offset
34h.
Interrupt Status (IS) — RO. This bit reflects the state of the INTx# signal at the
input of the enable/disable circuit. This bit is a 1 when the INTx# is asserted. This bit is
a 0 after the interrupt is cleared (independent of the state of the Interrupt Disable bit
in the command register).
Reserved
Revision ID (RID) — RO. This field indicates the device specific revision identifier.
Programming Interface (PI) — RO. ICH8 Thermal logic has no standard
programming interface.
setting of bit 6 in the Command register.
0010h
00h
00h
–
07h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/WC, RO
16 bits
RO
8 bits
RO
8 bits
791