NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 750

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.1.3
750
HSFC—Hardware Sequencing Flash Control Register
(
Memory Address:SPIBAR + 06h
Default Value:
SPI Memory Mapped Configuration Registers
13:8
7:3
2:1
Bit
Bit
15
14
0
0
Flash Cycle Done (FDONE) — R/W/C. The ICH8 sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset. When this bit is set and the SPI
SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block.
Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for
a new programmed access.
Hardware reset is initiated by one of the following resets:
Flash SPI SMI# Enable (FSMIE): — R/W. When set to 1, the SPI asserts an SMI#
request whenever the Flash Cycle Done bit is 1.
Reserved
Flash Data Byte Count (FDBC): — R/W. This field specifies the number of bytes to
shift in or out during the data portion of the SPI cycle. The contents of this register are
0’s based with 0b representing 1 byte and 111111b representing 64 bytes. The number
of bytes transferred is the value of this field plus 1.
This field is ignored for the Block Erase command.
Reserved
FLASH Cycle (FCYCLE). — R/W. This field defines the Flash SPI cycle type generated
to the FLASH when the FGO bit is set as defined below:
00 = Read (1 up to 64 bytes by setting FDBC)
01 = Reserved
10 = Write (1 up to 64 bytes by setting FDBC)
11 = Block Erase
Flash Cycle Go (FGO): — R/W/S. A write to this register with a 1 in this bit initiates a
request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware
when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the
cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO
bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be
ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
non-ME systems.
ME enabled systems.
0000h
Description
Description
Attribute:
Size:
)
Serial Peripheral Interface (SPI)
R/W, R/WS
16 bits
Intel
®
ICH8 Family Datasheet