NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 487

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.1.34
Intel
®
ICH8 Family Datasheet
PCS—Port Control and Status Register (SATA–D31:F2)
Address Offset: 92h
Default Value:
By default, the SATA ports are set to the disabled state (bits [5:0] = ‘0’). When enabled
by software, the ports can transition between the on, partial, and slumber states and
can detect devices. When disabled, the port is in the “off” state and cannot detect any
devices.
If an AHCI-aware or RAID enabled operating system is being booted then system BIOS
shall ensure that all supported SATA ports are enabled prior to passing control to the
OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner
for the individual SATA ports. This is accomplished by manipulating a port’s PxSCTL and
PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of
the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-
boot software must ensure that these bits are set to ‘1’ prior to booting the OS,
regardless as to whether or not a device is currently on the port.
Bits
15
14
13
12
11
10
9
OOB Retry Mode (ORM) — R/W.
0 = The SATA controller will not retry after an OOB failure
1 = The SATA controller will continue to retry after an OOB failure until successful
Reserved.
Port 5 Present (P5P) — RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled via P5E. This bit is not cleared upon surprise removal
of a device.
0 = No device detected.
1 = The presence of a device on Port 3 has been detected.
Port 4 Present (P4P) — RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled via P4E. This bit is not cleared upon surprise removal
of a device.
0 = No device detected.
1 = The presence of a device on Port 3 has been detected.
Port 3 Present (P3P) — RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled via P3E. This bit is not cleared upon surprise removal
of a device.
0 = No device detected.
1 = The presence of a device on Port 3 has been detected.
Port 2 Present (P2P) — RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled via P2E. This bit is not cleared upon surprise removal
of a device.
0 = No device detected.
1 = The presence of a device on Port 2 has been detected.
Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled via P1E. This bit is not cleared upon surprise removal
of a device.
0 = No device detected.
1 = The presence of a device on Port 1 has been detected.
(infinite retry)
0000h
–
93h
Description
Attribute:
Size:
R/W, R/WC, RO
16 bits
487