NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 751

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
20.1.4
20.1.5
20.1.6
Intel
®
ICH8 Family Datasheet
FADDR—Flash Address Register
(
Memory Address:SPIBAR + 08h
Default Value:
FDATA0—Flash Data 0 Register
(
Memory Address:SPIBAR + 10h
Default Value:
FDATAN—Flash Data [N] Register
(
Memory Address:SPIBAR + 14h
Default Value:
31:25
SPI Memory Mapped Configuration Registers
SPI Memory Mapped Configuration Registers
SPI Memory Mapped Configuration Registers
24:0
31:0
31:0
Bit
Bit
Bit
Reserved
Flash Linear Address (FLA): — R/W. The FLA is the starting byte linear address of a
SPI Read or Write cycle or an address within a Block for the Block Erase command. The
Flash Linear Address must fall within a region for which BIOS has access permissions.
Hardware must convert the FLA into a Flash Physical Address (FPA) before running this
cycle on the SPI bus.
Flash Data 0 (FD0): — R/W. This field is shifted out as the SPI Data on the Master-
Out Slave-In Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed
by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in
terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24
Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always
represents the value specified by the cycle address.
Note that the data in this register may be modified by the hardware during any
programmed SPI transaction. Direct Memory Reads do not modify the contents of this
register.
Flash Data N (FD[N]): — R/W. Similar definition as Flash Data 0. However, this
register does not begin shifting until FD[N-1] has completely shifted in/out.
00000000h
00000000h
SPIBAR + 18h
SPIBAR + 1Ch
SPIBAR + 20h
SPIBAR + 24h
SPIBAR + 28h
SPIBAR + 2Ch
SPIBAR + 30h
SPIBAR + 34h
SPIBAR + 38h
SPIBAR + 3Ch
SPIBAR + 40h
SPIBAR + 44h
SPIBAR + 48h
SPIBAR + 4Ch
00000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
)
)
)
R/W
32 bits
R/W
32 bits
R/W
32 bits
751