NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 542

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.1.4
Note:
13.1.5
542
PCISTS — PCI Status Register (SATA–D31:F5)
Address Offset: 06h
Default Value:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
RID—Revision Identification Register (SATA—D31:F5)
Offset Address: 08h
Default Value:
10:9
7:0
Bit
2:0
Bit
15
14
13
12
11
8
7
6
5
4
3
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
Reserved as 0 — RO.
Signaled Target Abort (STA) — RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED) — RO. For ICH8, this bit can only be set on read
completions received from SiBUS where there is a parity error.
1 = SATA controller, as a master, either detects a parity error or sees the parity error
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 1.
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities
list. The minimum requirement for the capabilities list must be PCI power management
for the SATA controller.
Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the
1 = Interrupt is to be asserted
Reserved
line asserted, and the parity error response bit (bit 6 of the command register) is
set.
command register [offset 04h]).
02B0h
See bit description
–
07h
®
Description
Description
I/O Controller Hub 8 (ICH8) Family Specification
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F5)
R/WC, RO
16 bits
RO
8 bits
Intel
®
ICH8 Family Datasheet