NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 155

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Table 58.
Note:
Warning:
5.12
5.12.1
5.12.1.1
Intel
®
ICH8 Family Datasheet
Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
The GPI strap technique to clear CMOS requires multiple steps to implement. The
system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again.
Clearing CMOS, using a jumper on VccRTC, must not be implemented.
Processor Interface (D31:F0)
The ICH8 interfaces to the processor with a variety of signals
Most ICH8 outputs to the processor use standard buffers. The ICH8 has separate
V
thus determines VOH for the outputs to the processor.
Processor Interface Signals
This section describes each of the signals that interface between the ICH8 and the
processor(s). Note that the behavior of some signals may vary during processor reset,
as the signals are used for frequency strapping.
A20M# (Mask A20)
The A20M# signal is active (low) when both of the following conditions are true:
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).
NEWCENTURY_STS
Intruder Detect
(INTRD_DET)
Top Swap (TS)
PATA Reset State (PRS)
(Mobile Only)
_CPU_IO
• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,
• Standard Input from processor: FERR#
• Intel SpeedStep
• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0
IGNNE#, CPUSLP#, CPUPWRGD
configurations)
Bit Name
signals that are pulled up at the system level to the processor voltage, and
®
technology output to processor: CPUPWRGOOD (In mobile
TCO1 Status Register
(TCO1_STS)
TCO2 Status Register
(TCO2_STS)
Backed Up Control
Register (BUC)
Backed Up Control
Register (BUC)
Register
TCOBase + 04h
TCOBase + 06h
Chipset Configuration
Registers:Offset 3414h
Chipset Configuration
Registers:Offset 3414h
Location
Bit(s)
7
0
0
1
Default
State
0
0
X
1
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