NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 462

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2
Table 120.
11.2.1
462
Bus Master IDE I/O Registers (IDE—D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA
register, located in Device 31:Function 1 Configuration space, offset 20h. All bus
master IDE I/O space registers can be accessed as byte, word, or dword quantities.
Reading reserved bits returns an indeterminate, inconsistent value, and writes to
reserved bits have no affect (but should not be attempted). The description of the I/O
registers is shown in
Bus Master IDE I/O Registers
BMICP—Bus Master IDE Command Register
(IDE—D31:F1)
Address Offset:
Default Value:
BMIBASE
+ Offset
7:4
2:1
Bit
04–07
3
0
00
01
02
03
Reserved. Returns 0.
Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master
transfer: This bit must NOT be changed when the bus master function is active.
0 = Memory reads
1 = Memory writes
Reserved. Returns 0.
Start/Stop Bus Master (START) — R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped
1 = Enables bus master operation of the controller. Bus master operation does not actually start
NOTE: This bit is intended to be cleared by software after the data transfer is
and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus
Master IDE Active bit (BMIBASE + 02h, bit 0) of the Bus Master IDE Status register for that IDE
channel is set) and the drive has not yet finished its data transfer (the Interrupt bit (BMIBASE
+ 02h, bit 2) in the Bus Master IDE Status register for that IDE channel is not set), the bus
master command is said to be aborted and data transferred from the drive may be discarded
instead of being written to system memory.
unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus
master operation begins when this bit is detected changing from 0 to 1. The controller will
transfer data between the IDE device and memory only when this bit is set. Master operation
can be halted by writing a 0 to this bit.
Mnemonic
BMIDP
BMICP
BMISP
completed, as indicated by either the Bus Master IDE Active bit being cleared or
the Interrupt bit of the Bus Master IDE Status register for that IDE channel
being set, or both. Hardware does not clear this bit automatically.
—
—
BMIBASE + 00h
00h
Table
Bus Master IDE Command Primary
Reserved
Bus Master IDE Status Primary
Reserved
Bus Master IDE Descriptor Table Pointer
Primary
120.
Register Name
Description
Attribute:
Size:
IDE Controller Registers (D31:F1) (Mobile Only)
8 bits
R/W
Intel
xxxxxxxxh
Default
®
ICH8 Family Datasheet
00h
00h
00h
00h
R/WC
Type
R/W,
R/W
R/W
RO
RO