NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 481

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.1.26
Intel
®
ICH8 Family Datasheet
PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset: 70h
Default Value:
11:8
15:8
Bits
7:4
Bit
7:0
13
12
3
2
1
0
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in
conjunction with the PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100
timings for the Primary Slave drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in
conjunction with the PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100
timings for the Primary Master drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this
Reserved
Scratchpad (SP1). ICH8 does not perform any action on these bits.
Secondary Drive 1 Base Clock (SCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Secondary Drive 0 Base Clock (SCBO) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 1 Base Clock (PCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 0 Base Clock (PCB0) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Next Capability (NEXT) — RO.
00h — if SCC = 01h (IDE mode).
A8h — for all other values of SCC to point to the next capability structure.
Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
register).
register).
XX01h
–
71h
Description
Description
Attribute:
Size:
RO
16 bits
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