NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 766

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.2.2.2
766
FLILL—Flash Invalid Instructions Register
(Flash Descriptor Memory Mapped Configuration Registers)
Memory Address:FCBA + 004h
16:06
5:3
2:0
31:24
23:16
15:8
7:0
Bits
Bits
Reserved
Component 2 Density: This field identifies the size of the 2nd Flash component. If
there is not 2nd Flash component, the contents of this field are undefined.
Valid Bit Settings:
000 = 512 KB
001 = 1 MB
010 = 2 MB
011 = 4 MB
100 = 8 MB
101 = 16 MB
111 = Reserved
Component 1 Density: This field identifies the size of the 1st or only Flash component.
Valid Bit Settings:
000 = 512 KB
001 = 1 MB
010 = 2 MB
011 = 4 MB
100 = 8 MB
101 = 16 MB
111 = Reserved
This field is defaulted to "101b" (16MB) after reset. In non-descriptor mode, only one
flash component is supported and all accesses to flash will be to this component.
Invalid Instruction 3: See definition of Invalid Instruction 0
Invalid Instruction 2: See definition of Invalid Instruction 0
Invalid Instruction 1: See definition of Invalid Instruction 0
Invalid Instruction 0: Op-code for an invalid instruction in the that the Flash Controller
should protect against instructions such as Chip Erase. This byte should be set to 0 if
there are no invalid instructions to protect against for this field. Op-codes programmed
in the Software Sequencing Opcode Menu Configuration and Prefix-Opcode
Configuration are not allowed to use any of the Invalid Instructions listed in this
register.
Description
Description
Size:
Serial Peripheral Interface (SPI)
32 bits
Intel
®
ICH8 Family Datasheet