NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 80
NH82801HBM S LB9A
Manufacturer Part Number
NH82801HBM S LB9A
Description
CONTROLLER HUB, ICH8M, I/O, 82801HBM
Manufacturer
Intel
Datasheet
1.NH82801HBM_S_LB9A.pdf
(890 pages)
Specifications of NH82801HBM S LB9A
Power Dissipation Pd
2.4W
Digital Ic Case Style
BGA
No. Of Pins
676
Pci Bus Type
I/O Controller Hub
Pci Express Base Spec
PCIe 1.1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 22.
2.19
Table 23.
80
Miscellaneous Signals (Sheet 2 of 2)
Intel
Intel
(Desktop Only) /
(Desktop Only) /
(Desktop Only) /
(Desktop Only) /
(Desktop Only) /
HDA_BIT_CLK
(Mobile Only)
(Mobile Only)
(Mobile Only)
(Mobile Only)
(Mobile Only)
(Mobile Only)
(Mobile Only)
HDA_RST#
HDA_SYNC
CL_DATA1
CL_VREF1
DPRSTP#
CL_CLK1
DPSLP#
®
Name
Name
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
High Definition Audio Link Signals (Sheet 1 of 2)
®
High Definition Audio Link
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
Test Point 1: Route signal to a test point.
Test Point 2: Route signal to a test point.
Test Point 3: Route signal to a test point.
Test Point 4: Route signal to a test point.
Test Point 5: Route signal to a test point.
Test Point 6: Route signal to a test point.
Test Point 7: Route signal to a test point.
Test Point 8: Route signal to a test point.
Intel
hardware reset to external codec(s).
Intel High Definition Audio Sync: This signal is a 48 kHz fixed
rate sample sync to the codec(s). Also used to encode the stream
number.
NOTE: HDA_SYNC is sampled at the rising edge of PWROK as a
Intel High Definition Audio Bit Clock Output: 24.000 MHz
serial data clock generated by the Intel High Definition Audio
controller (the Intel
down resistor.
®
functional strap. See
is a weak integrated pull-down resistor on the HDA_SYNC
pin.
High Definition Audio Reset: This signal is a master
®
ICH8). This signal has a weak internal pull-
Description
Description
Section 2.26.1
Intel
for more details. There
®
ICH8 Family Datasheet
Signal Description
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