NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 449

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDE Controller Registers (D31:F1) (Mobile Only)
11.1.3
Intel
®
ICH8 Family Datasheet
PCICMD—PCI Command Register (IDE—D31:F1)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable (ID) — R/W.
0 = Enables the IDE controller to assert INTA# (native mode) or IRQ14/15 (legacy mode).
1 = Disable. The interrupt will be deasserted.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. Controls the ICH8M’s ability to act as a PCI master
for IDE Bus Master transfers.
Memory Space Enable (MSE) — R/W.
0 = Disables access.
1 = Enables access to the IDE Expansion memory range. The EXBAR register (Offset 24h) must be
NOTE: BIOS should set this bit to a 1.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
1 = Enable. Note that the Base Address register for the Bus Master registers should be
NOTES:
programmed before this bit is set.
Bus Master IO registers.
programmed before this bit is set.
1.Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to
independently disable the Primary or Secondary I/O spaces.
2.When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin
Register (see
asserted).
If an interrupt occurs while the masking is in place and the interrupt is still
active when the masking ends, the interrupt will be allowed to be asserted.
04h
00h
–
05h
Section
11.1.19) will be masked (the interrupt will not be
Description
Attribute:
Size:
RO, R/W
16 bits
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