NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 600

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.1.28
Note:
600
SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F7, D26:F7)
Address Offset:
Default Value:
Power Well:
These bits are not reset by a D3-to-D0 warm rest or a core well reset.
31:28 (D29)
31:26 (D26)
27:22 (D29)
25:22 (D26)
15:14
13:6
Bit
21
20
19
18
17
16
5
4
Reserved — RO. Hardwired to 00h
SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
1 = Bits 27:22, 25:22 correspond to the Port Owner bits for ports 1 (22) through
SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.
0 = Power State bits Not modified.
1 = Software modified the Power State bits in the Power Management Control/
SMI on Async — R/WC. Software clears these bits by writing a 1 to it.
0 = No Async Schedule Enable bit change
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
SMI on Periodic — R/WC. Software clears this bit by writing a 1 it.
0 = No Periodic Schedule Enable bit change.
1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.
SMI on CF — R/WC. Software clears this bit by writing a 1 it.
0 = No Configure Flag (CF) change.
1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.
SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it.
0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being
1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).
SMI on HCReset — R/WC. Software clears this bit by writing a 1 it.
0 = HCRESET did Not transitioned to 1.
1 = HCRESET transitioned to 1.
Reserved — RO. Hardwired to 00h
SMI on PortOwner Enable — R/W.
0 = Disable.
1 = Enable. When any of these bits are 1 and the corresponding SMI on
SMI on PMSCR Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller
SMI on Async Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will
Suspend
00000000h
70h
4 (25) or 6 (27). These bits are set to 1 when the associated Port Owner bits
transition from 0 to 1 or 1 to 0.
Status (PMCSR) register (D29:F7, D26:F7:54h).
cleared).
PortOwner bits are 1, then the host controller will issue an SMI. Unused
ports should have their corresponding bits cleared.
will issue an SMI.
issue an SMI
–
73h
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
R/W, R/WC
32 bits
Intel
®
ICH8 Family Datasheet