NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 780

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.4
20.3.5
780
FADDR—Flash Address Register
(
Memory Address:GLBAR + 08h
Default Value:
FDATA0—Flash Data 0 Register
(
Memory Address:GLBAR + 10h
Default Value:
31:25
GbE LAN Memory Mapped Configuration Registers
GbE LAN Memory Mapped Configuration Registers
24:0
31:0
7:3
2:1
Bit
Bit
Bit
0
Reserved
FLASH Cycle (FCYCLE). — R/W. This field defines the Flash SPI cycle type generated
to the FLASH when the FGO bit is set as defined below:
00 = Read (1 up to 4 bytes by setting FDBC)
01 = Reserved
10 = Write (1 up to 4 bytes by setting FDBC)
11 = Block Erase
Flash Cycle Go (FGO): — R/W/S. A write to this register with a ‘1’ in this bit initiates
a request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware
when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the
cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO
bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be
ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
Reserved
Flash Linear Address (FLA): — R/W. The FLA is the starting byte linear address of a
SPI Read or Write cycle or an address within a Block for the Block Erase command. The
Flash Linear Address must fall within a region for which BIOS has access permissions.
Flash Data 0 (FD0): — R/W. This field is shifted out as the SPI Data on the Master-
Out Slave-In Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed
by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in
terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24
Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always
represents the value specified by the cycle address.
Note that the data in this register may be modified by the hardware during any
programmed SPI transaction. Direct Memory Reads do not modify the contents of this
register.
00000000h
00000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Serial Peripheral Interface (SPI)
R/W
32 bits
R/W
32 bits
)
)
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®
ICH8 Family Datasheet