NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 241

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.21.1.4.2
5.21.1.5
5.21.1.6
Intel
®
ICH8 Family Datasheet
Surprise Undock
Interaction Between Dock/Undock and Power Management States
When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for
initiating the docking sequence if the dock is already attached when PLTRST# is de-
asserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver de-
asserting CRTS# and detecting and enumerating the codecs attached to the
HDA_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware
signal indicating that a dock is attached. Therefore a method outside the scope of this
document must be used to cause the POST BIOS to initiate the docking sequence.
When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the
DCKCTL.DA bit is not cleared. The dock state machine will be reset such that
HDA_DOCK_EN# will be de-asserted, HDA_DOCK_RST# will be asserted and the
DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted,
the dock state machine will detect that DCKCTL.DA is set to “1” and will begin
sequencing through the dock process. Note that this does not require any software
intervention.
Relationship between HDA_DOCK_RST# and HDA_RST#
HDA_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As
long as HDA_RST# is asserted, the DOCK_RST# signal will also be asserted.
When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to
their default state (0's), and the dock state machine will be reset such that
HDA_DOCK_EN# will be de-asserted, and HDA_DOCK_RST# will be asserted. After any
PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and
then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting
CRST#.
When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state
machine will be reset such that HDA_DOCK_EN# will be de-asserted,
HDA_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this
state. When the CRST# bit is de-asserted, the dock state machine will detect that
DCKCTL.DA is set to “1” and will begin sequencing through the dock process. Note that
this does not require any software intervention.
1. In the surprise undock case the user undocks before software has had the
2. A signal on the docking connector is connected to the switch that isolates the dock
3. The undock event is communicated to the ACPI BIOS via ACPI control methods that
4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD
5. The HD Audio controller hardware is oblivious to the fact that a surprise undock
opportunity to gracefully halt the stream to the dock codec and initiate the
hardware undock sequence.
codec signals from the ICH8 HD Audio link signals (DOCK_DET# in the conceptual
diagram). When the undock event begins to occur the switch will be put into isolate
mode.
are outside the scope of this section of the document.
Audio Bus Driver via plug-N-play IRP. The Bus Driver then posthumously cleans up
the dock codec stream.
occurred. The flow from this point on is identical to the normal undocking sequence
described in section 0 starting at step 3). It finishes with the hardware clearing the
DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is
now ready for a subsequent docking event.
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