NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 190

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 79.
5.15.1.2
5.15.1.3
5.15.1.4
190
Shutdown latency is incurred after outstanding scheduled IDE data port transactions
(either a non-empty write post buffer or an outstanding read prefetch cycles) have
completed and before other transactions can proceed. It provides hold time on the
DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and
DIOW#). Shutdown latency is two PCI clocks in duration.
The IDE timings for various transaction types are shown in
IORDY Masking
The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point
(ISP) on a drive by drive basis via the IDETIM Register.
PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two
back-to-back 16-bit transactions to the IDE data port. The 32-bit data port feature is
enabled for all timings, not just enhanced timing. For compatible timings, a shutdown
and startup latency is incurred between the two, 16-bit halves of the IDE transaction.
This assures that the chip selects are deasserted for at least two PCI clocks between
the two cycles.
PIO IDE Data Port Prefetching and Posting
The ICH8 can be programmed via the IDETIM registers to allow data to be posted to
and prefetched from the IDE data ports.
Data prefetching is initiated when a data port read occurs. The read prefetch eliminates
latency to the IDE data ports and allows them to be performed back-to-back for the
highest possible PIO data transfer rates. The first data port read of a sector is called the
demand read. Subsequent data port reads from the sector are called prefetch reads.
The demand read and all prefetch reads much be of the same size (16 or 32 bits) –
software must not mix 32-bit and 16-bit reads.
Data posting is performed for writes to the IDE data ports. The transaction is completed
on the PCI bus after the data is received by the ICH8. The ICH8 then runs the IDE cycle
to transfer the data to the drive. If the ICH8 write buffer is non-empty and an unrelated
(non-data or opposite channel) IDE transaction occurs, that transaction will be stalled
until all current data in the write buffer is transferred to the drive. Only 16-bit buffer
writes are supported.
IDE Transaction Timings (PCI Clocks)
Non-Data Port Compatible
Data Port Compatible
Fast Timing Mode
IDE Transaction Type
Latency
Startup
4
3
2
Point (ISP)
Sample
IORDY
2–5
11
6
Recovery Time
Table
(RCT)
Intel
1–4
22
14
79.
®
Functional Description
ICH8 Family Datasheet
Shutdown
Latency
2
2
2