NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 111

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.1.2.7
5.1.3
5.1.4
Intel
®
ICH8 Family Datasheet
Memory and I/O Decode to PCI
The PCI bridge in the ICH8 is a subtractive decode agent, which follows the following
rules when forwarding a cycle from DMI to the PCI interface:
Parity Error Detection and Generation
PCI parity errors can be detected and reported. The following behavioral rules apply:
PCIRST#
The PCIRST# pin is generated under two conditions:
The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but
not other agents in the system.
• The PCI bridge will positively decode any memory/IO address within its window
• The PCI bridge will subtractively decode any 64-bit memory address not claimed
• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by
• If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively
• If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively
• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE
• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) and one of the
• If an address or command parity error is detected on PCI and PCICMD.SEE
• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is
• When bad parity is detected from DMI, bad parity will be driven on all data the
• When an address parity error is detected on PCI, the PCI bridge will never claim the
• PLTRST# active
• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1
registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory
windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows.
by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.
another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) set
forward from primary to secondary called out ranges in the IO window per PCI
Local Bus Specification (I/O transactions addressing the last 768 bytes in each,
1-KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively
assuming the above rules.
forward from primary to secondary I/O and memory ranges as called out in the PCI
Bridge Specification, assuming the above rules are met.
(D30:F0:Offset 1Eh:bit 15).
parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD
(D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#.
(D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1)
are all set, the bridge will set the PSTS.SSE (D30:F0:Offset 06h:bit 14) and
generate an internal SERR#.
set, the bridge will generate an internal SERR#
bridge.
cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle
should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept
of address parity error, so claiming the cycle could result in the rest of the system
seeing a bad transaction as a good transaction.
— During a write cycle, the PERR# signal is active, or
— A data parity error is detected while performing a read cycle
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