NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 174

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.13.9
5.13.9.1
Note:
Table 71.
Note:
Note:
174
Event Input Signals and Their Usage
The ICH8 has various input signals that trigger specific events. This section describes
those signals and how they should be used.
PWRBTN# (Power Button)
The ICH8 PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16
ms de-bounce on the input. The state transition descriptions are included in
Note that the transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to Power Button Override
Function section below for further detail.
Transitions Due to Power Button
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state
(S0–S4), even if PWROK is not active. In this case, the transition to the G2/S5 state
should not depend on any particular response from the processor (e.g., a Stop-Grant
cycle), nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable via the
PWRBTN_LVL bit.
The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the ICH8 is in a S0 state. If the
PWRBTN# signal is asserted and held active when the system is in a suspend state
(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0
state, the 4-second timer starts.
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Present
S1–S5
S0–S4
State
S0/Cx
G3
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
PWRBTN# held low
for at least 4
consecutive seconds
Event
SMI# or SCI generated
(depending on SCI_EN,
PWRBTN_INIT_EN,
PWRBTN_EN and
GLB_SMI_EN)
Wake Event. Transitions to
S0 state
None
Unconditional transition to
S5 state
Transition/Action
Software typically initiates a
Sleep state
Standard wakeup
No effect since no power
Not latched nor detected
No dependence on processor
(e.g., Stop-Grant cycles) or
any other subsystem
Intel
®
Functional Description
Comment
ICH8 Family Datasheet
Table
71.