NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 561

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F5)
13.2.3.3
Intel
®
ICH8 Family Datasheet
PxSERR—Serial ATA Error Register (D31:F5)
Address Offset: BAR + 02h
Default Value:
31:16
Bit
Diagnostics (DIAG) — R/WC. Contains diagnostic error information for use by
diagnostic software in validating correct operation or isolating failure modes:
Bits
31:27
26
25
24
23
22
21
20
19
18
17
16
Reserved
Exchanged (X): When set to one this bit indicates a COMINIT signal was
received. This bit
is reflected in the interrupt register PxIS.PCS.
Unrecognized FIS Type (F): Indicates that one or more FISs were received
by the Transport layer with good CRC, but had a type field that was not
recognized.
Transport state transition error (T): Indicates that an error has occurred in
the transition from one state to another within the Transport layer since the last
time this bit was cleared.
Link Sequence Error (S): Indicates that one or more Link state machine
error conditions was encountered. The Link Layer state machine defines the
conditions under which the link layer detects an erroneous transition.
Handshake Error (H): Indicates that one or more R_ERR handshake
response was received in response to frame transmission. Such errors may be
the result of a CRC error detected by the recipient, a disparity or 8b/10b
decoding error, or other error condition leading to a negative handshake on a
transmitted frame.
CRC Error (C): Indicates that one or more CRC errors occurred with the Link
Layer.
Disparity Error (D): This field is not used by AHCI.
10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding
errors occurred.
Comm Wake (W): Indicates that a Comm Wake signal was detected by the
Phy.
Phy Internal Error (I): Indicates that the Phy detected some internal error.
PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy
signal changed state since the last time this bit was cleared. In the ICH8, this
bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this
bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will
be generated if enabled. Software clears this bit by writing a 1 to it.
Description
00000000h
Description
Attribute:
Size:
R/WC
32 bits
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