NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 236

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 95.
5.20.7.2.1
236
Data Values for Slave Read Registers (Sheet 2 of 2)
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit –
Address– Write bit sequence. When the ICH8 detects that the address matches the
value in the Receive Slave Address register, it will assume that the protocol is always
followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In
other words, if a Start –Address–Read occurs (which is invalid for SMBus Read or Write
protocol), and the address matches the ICH8’s Slave Address, the ICH8 will still grab
the cycle.
Register
9 – FFh
5
6
7
8
Bits
6:4
7:0
7:0
7:0
7:0
2
3
7
0
1
2
3
5
6
7
DOA CPU Status. This bit will be 1 to indicate that the processor is dead
1 = SECOND_TO_STS bit set. This bit will be set after the second time-out
(SECOND_TO_STS bit) of the Watchdog Timer occurs.
Reserved. Will always be 0, but software should ignore.
Reflects the value of the GPI[11]/SMBALERT# pin (and is dependent upon
the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value
in this bit equals the level of the GPI[11]/SMBALERT# pin (high = 1,
low = 0).
If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse
of the level of the GPI[11]/SMBALERT# pin (high = 0, low = 1).
FWH bad bit. This bit will be 1 to indicate that the FWH read returned FFh,
which indicates that it is probably blank.
Battery Low Status. ‘1’ if the BATLOW# pin is a ‘0’.
CPU Power Failure Status: ‘1’ if the CPUPWR_FLR bit in the
GEN_PMCON_2 register is set.
INIT# due to receiving Shutdown message: This event is visible from
the reception of the shutdown message until a platform reset is done if the
Shutdown Policy Select bit (SPS) is configured to drive INIT#. When the
SPS bit is configured to generate PLTRST# based on shutdown, this register
bit will always return 0.
Events on signal will not create a event message
POWER_OK_BAD: Indicates the failure core power well ramp during boot/
resume. This bit will be active if the SLP_S3# pin is de-asserted and
PWROK pin is not asserted.
Thermal Trip: This bit will shadow the state of CPU Thermal Trip status bit
(CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a
event message
Reserved: Default value is “X”
NOTE: Software should not expect a consistent value when this bit is read
Contents of the Message 1 register. See
this register.
Contents of the Message 2 register. See
this register.
Contents of the WDSTATUS register. See
this register.
Reserved
through SMBUS/SMLINK
Description
Section 9.9.8
Section 9.9.8
Section 9.9.9
Intel
®
Functional Description
for the description of
for the description of
for the description of
ICH8 Family Datasheet