NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 68

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11.
2.8
Table 12.
68
Serial ATA Interface Signals (Sheet 3 of 3)
IDE Interface (Mobile Only)
IDE Interface Signals (Mobile Only)
SATACLKREQ#
SLOAD/GPIO38
SDATAOUT0/
SDATAOUT1/
DD[15:0]
SATALED#
DA[2:0]
DCS1#
DCS3#
DDREQ
SCLOCK/
Name
/GPIO35
GPIO22
GPIO39
GPIO48
Name
Typ
I/O
O
O
O
e
I
(Native)/
(Native)/
(Native)/
I/O (GP)
I/O (GP)
I/O (GP)
I/O (GP)
(Native)
Type
OD
OD
OD
OD
OC
IDE Device Chip Selects for 100 Range: For ATA command register
block. This output signal is connected to the corresponding signal on the
IDE connector.
IDE Device Chip Select for 300 Range: For ATA control register block.
This output signal is connected to the corresponding signal on the IDE
connector.
IDE Device Address: These output signals are connected to the
corresponding signals on the IDE connector. They are used to indicate
which byte in either the ATA command block or control block is being
addressed.
IDE Device Data: These signals directly drive the corresponding signals
on the IDE connector. There is a weak internal pull-down resistor on DD7.
IDE Device DMA Request: This input signal is directly driven from the
DRQ signal on the IDE connector. It is asserted by the IDE device to
request a data transfer, and used in conjunction with the PCI bus master
IDE function and are not associated with any AT compatible DMA channel.
There is a weak internal pull-down resistor on this signal.
/
Serial ATA LED: This is an open-collector output pin driven during
SATA command activity. It is to be connected to external circuitry
that can provide the current to drive a platform LED. When active,
the LED is on. When tri-stated, the LED is off. An external pull-up
resistor to Vcc3_3 is required.
Note: This is sampled as a functional strap. See Strapping section
for details.
Serial ATA Clock Request: This is an open-drain output pin when
configured as SATACLKREQ#. It is to connect to the system clock
chip. When active, request for SATA Clock running is asserted.
When tri-stated, it tells the clock chip that SATA clock can be
stopped. An external pull-up resistor is required.
SGPIO Reference Clock: The SATA controller uses rising edges of
this clock to transmit serial data, and the target uses the falling
edge of this clock to latch data.
If SGPIO interface is not used, this signal can be used as a GPIO.
SGPIO Load: The controller drives a 1 at the rising edge of
SCLOCK to indicate either the start or end of a bit stream. A 4-bit
vendor specific pattern will be transmitted right after the signal
assertion.
If SGPIO interface is not used, this signal can be used as a GPIO.
SGPIO Dataout: Driven by the controller to indicate the drive
status in the following sequence: drive 0, 1, 2, n, 0, 1, 2, n, 2...
If SGPIO interface is not used, the signals can be used as GPIO.
Description
Description
Intel
®
ICH8 Family Datasheet
Signal Description