NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 690

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.37
690
SDSTS—Stream Descriptor Status Register
(Intel
Memory Address:Input Stream[0]: HDBAR + 83h
Default Value:
7:6
1:0
Bit
5
4
3
2
Reserved.
FIFO Ready (FIFORDY) — RO. For output streams, the controller hardware will set this
bit to 1 while the output DMA FIFO contains enough data to maintain the stream on the
link. This bit defaults to 0 on reset because the FIFO is cleared on a reset.
For input streams, the controller hardware will set this bit to 1 when a valid descriptor
is loaded and the engine is ready for the RUN bit to be set.
Descriptor Error — R/WC.
0 = No error
1 = Serious error occurred during the fetch of a descriptor. This could be a result of a
Software may attempt to restart the stream engine after addressing the cause of the
error and writing a 1 to this bit to clear it.
FIFO Error — R/WC. The bit is cleared by writing a 1 to it.
0 = No error
1 = FIFO error occurred. This bit is set even if an interrupt is not enabled.
For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set.
When this happens, the FIFO pointers do not increment and the incoming data is not
written into the FIFO, thereby being lost.
For an output stream, this indicates a FIFO underrun when there are still buffers to
send. The hardware should not transmit anything on the link for the associated stream
if there is not valid data to send.
Buffer Completion Interrupt Status — R/WC.
0 = Last sample of buffer Not processed.
1 = Set by the hardware after the last sample of a buffer has been processed, AND if
Reserved.
®
High Definition Audio Controller—D27:F0)
Master Abort, a parity or ECC error on the bus, or any other error that renders the
current Buffer Descriptor or Buffer Descriptor list useless. This error is treated as a
fatal stream error, as the stream cannot continue running. The RUN bit will be
cleared and the stream will stopped.
the Interrupt on Completion bit is set in the command byte of the buffer descriptor.
It remains active until software clears it by writing a 1 to it.
Input Stream[1]: HDBAR + A3h
Input Stream[2]: HDBAR + C3h
Input Stream[3]: HDBAR + E3h
Output Stream[0]: HDBAR + 103h
Output Stream[1]: HDBAR + 123h
Output Stream[2]: HDBAR + 143h
Output Stream[3]: HDBAR + 163h
00h
Intel
®
Description
High Definition Audio Controller Registers (D27:F0)
Size:
Attribute:R/WC, RO
8 bits
Intel
®
ICH8 Family Datasheet