NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 606

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.1.4
606
HCCPARAMS—Host Controller Capability Parameters
Register
Offset:
Default Value:
31:16
15:8
7:4
Bit
3
2
1
0
Reserved
EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h,
indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI
configuration space.
Isochronous Scheduling Threshold — RO. This field indicates, relative to the current
position of the executing host controller, where software can reliably update the
isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates
the number of micro-frames a host controller hold a set of isochronous data structures
(one or more) before flushing the state. When bit 7 is a 1, then host software assumes
the host controller may cache an isochronous data structure for an entire frame. Refer
to the EHCI specification for details on how software uses this information for
scheduling isochronous transfers.
This field is hardwired to 7h.
Reserved. These bits are reserved and should be set to 0.
Asynchronous Schedule Park Capability — RO. This bit is hardwired to 0 indicating that
the host controller does not support this optional feature
Programmable Frame List Flag — RO.
0 = System software must use a frame list length of 1024 elements with this host
1 = System software can specify and use a smaller frame list and configure the host
64-bit Addressing Capability — RO. This field documents the addressing range
capability of this implementation. The value of this field determines whether software
should use the 32-bit or 64-bit data structures. Values for this field have the following
interpretation:
0 = Data structures using 32-bit address memory pointers
1 = Data structures using 64-bit address memory pointers
This bit is hardwired to 1.
NOTE: ICH8 only implements 44 bits of addressing. Bits 63:44 will always be 0.
controller. The USB2.0_CMD register (D29:F7, D26:F7:CAPLENGTH + 20h, bits
3:2) Frame List Size field is a read-only register and must be set to 0.
controller via the USB2.0_CMD register Frame List Size field. The frame list must
always be aligned on a 4K page boundary. This requirement ensures that the frame
list is always physically contiguous.
MEM_BASE + 08h
00006871h
–
0Bh
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
RO
32 bits
Intel
®
ICH8 Family Datasheet