NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 426

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.10.5
9.10.6
426
GPO_BLINK—GPO Blink Enable Register
Offset Address: GPIOBASE +18h
Default Value:
Lockable:
NOTE: GPIO18 will blink by default immediately after reset. This signal could be connected to an
GP_SER_BLINK[31:0]—GP Serial Blink
Offset Address: GPIOBASE +1Ch
Default Value:
Lockable:
31:0
31:0
Bit
Bit
LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful
POST).
GP_BLINK[31:0] — R/W. The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will
The value of the corresponding GP_LVL bit remains unchanged during the blink
process, and does not effect the blink in any way. The GP_LVL bit is not altered
when programmed to blink. It will remain at its previous value.
These bits correspond to GPIO in the Resume well. These bits revert to the default
value based on RSMRST# or a write to the CF9h register (but not just on
PLTRST#).
GP_SER_BLINK[31:0]: The setting of this bit has no effect if the corresponding
GPIO is programmed as an input or if the corresponding GPIO has the GPO_BLINK
bit set.
When set to a 0, the corresponding GPIO will function normally.
When using serial blink, this bit should be set to a 1 while the corresponding
GP_IO_SEL bit is set to 1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK
bit ensures ICH8 will not drive a 1 on the pin as an output. When this
corresponding bit is set to a 1 and the pin is configured to output mode, the serial
blink capability is enabled. The ICH8 will serialize messages through an open-drain
buffer configuration.
The value of the corresponding GP_LVL bit remains unchanged and does not impact
the serial blink capability in any way.
Writes to this register have no effect when the corresponding pin is configured in
native mode and the read value returned is undefined.
blink at a rate of approximately once per second. The high and low times have
approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is
set.
00040000h
No
00000000h
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Intel
®
ICH8 Family Datasheet