NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 427

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.7
9.10.8
Intel
®
ICH8 Family Datasheet
GP_SB_CMDSTS[31:0]—GP Serial Blink Command Status
Offset Address: GPIOBASE +20h
Default Value:
Lockable:
GP_SB_DATA[31:0]—GP Serial Blink Data
Offset Address: GPIOBASE +24h
Default Value:
Lockable:
31:24
23:22
21:16
15:9
31:0
7:1
Bit
Bit
8
0
Reserved
Data Length Select (DLS): This read/write field determines the number of bytes
to serialize on GPIO.
00 = Serialize bits 7:0 of GP_SB_DATA (1 byte)
01 = Serialize bits 15:0 of GP_SB_DATA (2 bytes)
10 = Undefined - Software must not write this value
11 = Serialize bits 31:0 of GP_SB_DATA (4 bytes)
Software should not modify the value in this register unless the Busy bit is clear.
Writes to this register have no effect when the corresponding pin is configured in
native mode and the read value returned is undefined.
Data Rate Select (DRS): This read/write field selects the number of 128ns time
intervals to count between Manchester data transitions. The default of 8h results in
a 1024ns minimum time between transitions. A value of 0h in this register
produces undefined behavior.
Software should not modify the value in this register unless the Busy bit is clear.
Reserved
Busy: This read-only status bit is the hardware indication that a serialization is in
progress. Hardware sets this bit to 1 based on the Go bit being set. Hardware
clears this bit when the Go bit is cleared by the hardware.
Reserved
Go: This bit is set to 1 by software to start the serialization process. Hardware
clears the bit after the serialized data is sent. Writes of 0 to this register have no
effect. Software should not write this bit to 1 unless the Busy status bit is cleared.
GP_SB_DATA[31:0]: This read-write register contains the data serialized out.
The number of bits shifted out are selected through the DLS field in the
GP_SB_CMDSTS register. This register should not be modified by software when
the Busy bit is set.
00080000h
No
00000000h
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
32-bit
Core
R/W
32-bit
Core
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