NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 189

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.15
5.15.1
5.15.1.1
Intel
®
ICH8 Family Datasheet
IDE Controller (D31:F1) (Mobile Only)
The ICH8 IDE controller features one set of interface signals that can be enabled, tri-
stated or driven low.
The IDE interfaces of the ICH8 can support several types of data transfers:
PIO Transfers
The ICH8 IDE controller includes both compatible and fast timing modes. The fast
timing modes can be enabled only for the IDE data ports. All other transactions to the
IDE registers are run in single transaction mode with compatible timings.
Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1). The
IDE_TIMP and IDE_TIMS Registers permit different timing modes to be programmed
for drive 0 and drive 1 of the same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each
drive by programming the IDE I/O Configuration register and the Synchronous DMA
Control and Timing registers. When a drive is enabled for synchronous DMA mode
operation, the DMA transfers are executed with the synchronous DMA timings. The PIO
transfers are executed using compatible timings or fast timings if also enabled.
PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and
shutdown latency. Startup latency is incurred when a PCI master cycle targeting the
IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup
latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of
the read and write strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time.
Recovery time is provided so that transactions may occur back-to-back on the IDE
interface (without incurring startup and shutdown latency) without violating minimum
cycle periods for the IDE interface. The command strobe assertion width for the
enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,
or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set
to 1, 2, 3, or 4 PCI clocks.
If IORDY is asserted when the initial sample point is reached, no wait-states are added
to the command strobe assertion length. If IORDY is negated when the initial sample
point is reached, additional wait-states are added. Since the rising edge of IORDY must
be synchronized, at least two additional PCI clocks are added.
• Programmed I/O (PIO): Processor is in control of the data transfer.
• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although
• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both
• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both
• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both
it does not use the 8237 in the ICH8. This protocol off loads the processor from
moving data. This allows higher transfer rate of up to 16 MB/s.
host and target throttling of data and transfer rates of up to 33 MB/s.
host and target throttling of data and transfer rates of up to 66 MB/s.
host and target throttling of data and transfer rates of up to 100 MB/s.
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