NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 217

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.19.7.4
5.19.7.5
5.19.8
5.19.8.1
Intel
®
ICH8 Family Datasheet
ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
Mobile Considerations
The ICH8 USB 2.0 implementation does not behave differently in the mobile
configurations versus the desktop configurations. However, some features may be
especially useful for the mobile configurations.
Interaction with UHCI Host Controllers
The Enhanced Host controllers share its ports with UHCI Host controllers in the ICH8.
The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the
UHC at D29:F2 shares ports 4 and 5 with the EHC at D29:F7, while the UHC at D26:F0
shares ports 6 and 7, the UHC at D26:F1 shares ports 8 and 9 with EHC at D26:F7.
There is very little interaction between the Enhanced and the UHCI controllers other
than the multiplexing control which is provided as part of the EHC.
USB Port Connections at a conceptual level.
Port-Routing Logic
Integrated into the EHC functionality is port-routing logic, which performs the muxing
between the UHCI and EHCI host controllers. The ICH8 conceptually implements this
logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of
USB 2.0’s high-speed signaling protocol or if the EHCI software drivers are not present
as indicated by the Configured Flag, then the UHCI controller owns the port. Owning
the port means that the differential output is driven by the owner and the input stream
is only visible to the owner. The host controller that is not the owner of the port
internally sees a disconnected port.
• If a system (e.g., mobile) does not implement all ten USB 2.0 ports, the ICH8
• Mobile systems may want to minimize the conditions that will wake the system.
• Mobile systems may want to cut suspend well power to some or all USB ports when
provides mechanisms for changing the structural parameters of the EHC and hiding
unused UHCI controllers. See the Intel
how BIOS should configure the ICH8.
The ICH8 implements the “Wake Enable” bits in the Port Status and Control
registers, as specified in the EHCI spec, for this purpose.
in a low-power state. The ICH8 implements the optional Port Wake Capability
Register in the EHC Configuration Space for this platform-specific information to be
communicated to software.
— The System is always in the S0 state when the EHC is in the D0 state. However,
— When in D0, the Pause feature (See
— The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power
— All core well logic is reset in the S3/S4/S5 states.
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
processor low-power states to be entered.
turns off).
®
ICH8 BIOS Specification for information on
Section
5.19.7.1) enables dynamic
Figure 16
shows the
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