NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 679

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Intel
17.2.15
17.2.16
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
WALCLK—Wall Clock Counter Register
(Intel
Memory Address:HDBAR + 30h
Default Value:
SSYNC—Stream Synchronization Register
(Intel
Memory Address:HDBAR + 34h
Default Value:
31:0
31:8
7:0
Bit
Bit
Wall Clock Counter — RO. This field provides results from a 32 bit counter that is
incremented on each link BCLK period and rolls over from FFFF FFFFh to 0000 0000h.
This counter will roll over to 0 with a period of approximately 179 seconds.
This counter is enabled while the BCLK bit is set to 1. Software uses this counter to
synchronize between multiple controllers. Will be reset on controller reset.
Reserved
Stream Synchronization (SSYNC) — R/W. When set to 1, these bits block data from
being sent on or received from the link. Each bit controls the associated stream
descriptor (i.e., bit 0 corresponds to the first stream descriptor, etc.)
To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits
for the associated stream descriptors are then set to 1 to start the DMA engines. When
all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at
the same time, and transmission or reception of bits to or from the link will begin
together at the start of the next full link frame.
To synchronously stop the streams, fist these bits are set, and then the individual RUN
bits in the stream descriptor are cleared by software.
If synchronization is not desired, these bits may be left as 0, and the stream will simply
begin running normally when the stream’s RUN bit is set.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0: input stream 1
Bit 1: input stream 2
Bit 2: input stream 3
Bit 3: input stream 4
Bit 4: output stream 1
®
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High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00000000h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
32 bits
R/W
32 bits
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