NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 74

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16.
74
Power Management Interface Signals (Sheet 3 of 4)
(Mobile Only) /
(Desktop Only)
(Desktop Only)
SUS_STAT# /
SYS_RESET#
(Mobile Only)/
MCH_SYNC#
VRMPWRGD
CK_PWRGD
LAN_RST#
RSMRST#
CLKRUN#
BMBUSY#
SUSCLK
WAKE#
LPCPD#
GPIO32
Name
GPIO0
Type
I/O
O
O
O
I
I
I
I
I
I
I
System Reset: This pin forces an internal reset after being
debounced. The ICH8 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before
forcing a reset on the system.
Resume Well Reset: This signal is used for resetting the resume
power plane logic. This signal must be asserted for at least 10 ms after
the suspend power wells are valid. When deasserted, this signal is an
indication that the suspend power wells are stable.
LAN Reset: When asserted, the internal LAN controller is in reset. This
signal must be asserted until the LAN power wells (VccLAN3_3 and
VccLAN1_05) and VccCL3_3 power well are valid. When deasserted,
this signal is an indication that the LAN power wells are stable.
NOTES:
1.
2.
3.
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.
MCH SYNC: This input is internally ANDed with the PWROK input. This
signal is connect to the ICH_SYNC# output of (G)MCH.
Suspend Status: This signal is asserted by the ICH8 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC interface.
Suspend Clock: This clock is an output of the RTC generator circuit to
use by other chips for refresh clock.
VRM Power Good: This signal should be connected to be the
processor’s VRM Power Good signifying the VRM is stable. This signal is
internally ANDed with the PWROK input.
This signal is in the resume well.
Clock Generator Power Good: indicates to the clock generator when
the main power well is valid. This signal is asserted high when both
SLP_S3# and VRMPWRGD are high.
Bus Master Busy: To support the C3 state. Indication that a bus
master device is busy. When this signal is asserted, the BM_STS bit will
be set. If this signal goes active in a C3 state, it is treated as a break
event.
NOTE: This signal is internally synchronized using the PCICLK and a
NOTE: In desktop configurations, this signal is a GPIO.
PCI Clock Run: This signal is used to support PCI CLKRUN protocol. It
connects to peripherals that need to request clock restart or prevention
of clock stopping.
LAN_RST# must not deassert before RSMRST# deasserts
LAN_RST# must not deassert after PWROK asserts.
If integrated LAN is not used LAN_RST# can be tied to Vss.
two-stage synchronizer. It does not need to meet any particular
setup or hold time.
Description
Intel
®
ICH8 Family Datasheet
Signal Description