NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 360

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.7
9.4.8
360
OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0)
Offset Address: Master Controller
Default Value:
OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller
Default Value:
Following a part reset or ICW initialization, the controller enters the fully nested mode
of operation. Non-specific EOI without rotation is the default. Both rotation mode and
specific EOI mode are disabled following initialization.
7:0
7:5
4:3
2:0
Bit
Bit
Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the
corresponding IRQ line is masked. When a 0 is written to any bit in this register, the
corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by
the controller. Masking IRQ2 on the master controller will also mask the interrupt
requests from the slave controller.
Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and
End of Interrupt modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
011 = *Specific EOI Command
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 = *Set Priority Command
111 = *Rotate on Specific EOI Command
*L0 – L2 Are Used
OCW2 Select — WO. When selecting OCW2, bits 4:3 = “00”
Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt
level acted upon when the SL bit is active. A simple binary code, outlined below, selects
the channel for the command to act upon. When the SL bit is inactive, these bits do not
have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case.
Code
000b
001b
010b
011b
Slave Controller
00h
Slave Controller
Bit[4:0]=undefined, Bit[7:5]=001
Interrupt Level
IRQ2/10
IRQ3/11
IRQ0/8
IRQ1/9
–
–
–
–
0A1h
0A0h
021h
020h
Description
Description
Attribute:
Size:
Attribute:
Size:
Code
000b
001b
010b
011b
LPC Interface Bridge Registers (D31:F0)
Interrupt Level
IRQ4/12
IRQ5/13
IRQ6/14
IRQ7/15
R/W
8 bits
WO
8 bits
Intel
®
ICH8 Family Datasheet