NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 170

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 67.
5.13.7.3
Note:
Table 68.
170
Sleep Types
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the
system to a full on state (S0), although some non-critical subsystems might still be
shut off and have to be brought back manually. For example, the hard disk may be shut
off during a sleep state, and have to be enabled via a GPIO pin before it can be used.
Upon exit from the ICH8-controlled Sleep states, the WAK_STS bit is set. The possible
causes of Wake Events (and their restrictions) are shown in
(Mobile Only) If the BATLOW# signal is asserted, ICH8 does not attempt to wake from
an S1–S5 state, even if the power button is pressed. This prevents the system from
waking when the battery power is insufficient to wake the system. Wake events that
occur while BATLOW# is asserted are latched by the ICH8, and the system wakes after
BATLOW# is deasserted.
Causes of Wake Events (Sheet 1 of 2)
RTC Alarm
Power Button
GPI[0:15]
Classic USB
LAN
RI#
Intel
Definition Audio
Primary PME#
Secondary PME#
Sleep
Type
®
S1
S3
S4
S5
Cause
High
Intel
signal. This lowers the processor’s power consumption. No snooping is possible in
this state.
ICH8 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical
circuits. Power is only retained to devices needed to wake from this sleeping state,
as well as to the memory.
ICH8 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to
the memory subsystem. Only devices needed to wake from this state should be
powered.
Same power state as S4. ICH8 asserts SLP_S3#, SLP_S4# and SLP_S5#.
®
S1–S5 (Note
Wake From
States Can
ICH8 asserts the STPCLK# signal. It also has the option to assert CPUSLP#
(Note 1)
(Note 1)
(Note 1)
S1–S5
S1–S5
S1–S5
S1–S5
S1–S5
S1–S5
S1–S5
S1–S5
1)
Set RTC_EN bit in PM1_EN register
Always enabled as Wake event
GPE0_EN register
NOTE: GPI’s that are in the core well are not capable of
Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in
GPE0_EN register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN register
Event Sets PME_B0_STS bit; PM_B0_EN must be enabled.
Can not wake from S5 state if it was entered due to power
failure or power button override.
PME_B0_EN bit in GPE0_EN register
Set PME_EN bit in GPE0_EN register.
waking the system from sleep states where the core
well is not powered.
Comment
How Enabled
Table
Intel
68.
®
Functional Description
ICH8 Family Datasheet