NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 743

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Precision Event Timer Registers
19.1.2
19.1.3
.
Intel
®
ICH8 Family Datasheet
GEN_CONF—General Configuration Register
Address Offset: 010h
Default Value:
GINTR_STA—General Interrupt Status Register
Address Offset: 020h
Default Value:
63:2
63:3
Bit
Bit
1
0
2
1
0
Reserved. These bits will return 0 when read.
Timer 2 Interrupt Active (T02_INT_STS) — R/W. Same functionality as Timer 0.
Timer 1 Interrupt Active (T01_INT_STS) — R/W. Same functionality as Timer 0.
Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit
depends on whether the edge or level-triggered mode is used for this timer.
(default = 0).
If set to level-triggered mode:
This bit will be set by hardware if the corresponding timer interrupt is active. Once the
bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0
to this bit will have no effect.
If set to edge-triggered mode:
This bit should be ignored by software. Software should always write 0 to this bit.
NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes
Reserved. These bits return 0 when read.
Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the
LEG_RT_CNF bit are both set, then the interrupts will be routed as follows:
Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the
timers to generate interrupts. If this bit is 0, then the main counter will halt (will not
increment) and no interrupts will be caused by any of these timers. For level-triggered
interrupts, if an interrupt is pending when the ENABLE_CNF bit is changed from 1 to 0,
the interrupt status indications (in the various Txx_INT_STS bits) will not be cleared.
Software must write to the Txx_INT_STS bits to clear the interrupts.
NOTE: This bit will default to 0. BIOS can set it to 1 or 0.
• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC
• Timer 2-n is routed as per the routing in the timer n config registers.
• If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC)
• If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers
• This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to
will have no impact.
are used.
disable the legacy replacement routing.
will have no effect.
00000000 00000000h
00000000 00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
64 bits
R/W, R/WC
64 bits
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