NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 341

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.28
9.1.29
Intel
®
ICH8 Family Datasheet
BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address: DCh
Default Value:
Lockable:
FDCAP—Feature Detection Capability ID
(LPC I/F—D31:F0)
Offset Address: E0h-E1h
Default Value:
4
3:2
15:8
7:0
7:5
Bit
Bit
1
0
Reserved
Top Swap Status (TSS)— RO: This bit provides a read-only path to view the state of
the Top Swap bit that is at offset 3414h, bit 0.
SPI Read Configuration (SRC)— R/W: This 2-bit field controls two policies related to
BIOS reads on the SPI interface:
Bit 3- Prefetch Enable
Bit 2- Cache Disable
Settings are summarized below:
BIOS Lock Enable (BLE) — R/WLO.
0 = Setting the BIOSWE will not cause SMIs.
1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be
BIOS Write Enable (BIOSWE) — R/W.
0 = Only read cycles result in Firmware Hub I/F cycles.
1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is
Next Item Pointer (NEXT): Configuration offset of the next Capability Item. 00h
indicates the last item in the Capability List.
Capability ID: Indicates a Vendor Specific Capability
Bits 3:2
cleared by a PLTRST#
written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is
generated. This ensures that only SMI code can update BIOS.
00b
01b
10b
11b
00h
No
0000h
Description
No prefetching, but caching enabled. 64B demand reads load
the read buffer cache with “valid” data, allowing repeated code
fetches to the same line to complete quickly
No prefetching and no caching. One-to-one correspondence of
host BIOS reads to SPI cycles. This value can be used to invalidate
the cache.
Prefetching and Caching enabled. This mode is used for long
sequences of short reads to consecutive addresses (i.e., shadowing).
Reserved. This is an invalid configuration, caching must be
enabled when prefetching is enabled.
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/WLO, R/W, RO
8 bit
Core
RO
16 bit
Core
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