D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 86

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 2.6
SH7729R CPU
MOV.W
ADD
........
.DATA.W H'1234
Note: Immediate data is referenced by @(disp,PC).
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly on memory.
Delayed Branching: Unconditional branch instructions, etc., are executed as delayed branches.
With a delayed branch instruction, the branch is made after execution of the instruction (called the
slot instruction) immediately following the delayed branch instruction. This minimizes disruption
of the pipeline when a branch is made.
With a delayed branch, the actual branch operation occurs after execution of the slot instruction.
However, instruction execution for register updating, etc., excluding the branch operation, is
performed in delayed branch instruction
the contents of the register holding the branch destination address are changed in the delay slot,
the branch destination address remains as the register contents prior to the change.
Table 2.7
SH7729R CPU
BRA
ADD
Multiply/Multiply-and-Accumulate Operations: A 16
executed in 1 to 3 states, and a 16
states. A 32
operation are each executed in 2 to 5 states.
Rev. 5.0, 09/03, page 38 of 806
TRGET
R1,R0
@(disp,PC),R1
R1,R0
Word Data Sign Extension
Delayed Branch Instructions
32
64 multiply operation and a 32
Description
ADD is executed before branch to
TRGET.
Description
R1 sign-extended to 32 bits,
becomes H'00001234, and is
then operated on by the ADD
instruction.
16 + 64
delay slot instruction order. For example, even though
64 multiply-and-accumulate operation in 2 to 3
32 + 64
16
Example of Other CPU
ADD.W R1,R0
BRA
Example of Other CPU
ADD.W
64 multiply-and-accumulate
32 multiply operation is
TRGET
#H'1234,R0