D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 377
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Company:
Part Number:
D6417729RHF200BV
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Burst Write: The timing chart for a burst write is shown in figure 11.17. In the SH7729R, a burst
write occurs in the event of cache write-back or 16-byte DMAC transfer. In a burst write
operation, following the Tr cycle in which ACTV command output is performed, a WRIT
command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-
precharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as
the write command. In case of the write with auto-precharge command, precharging of the
relevant bank is performed in the synchronous DRAM after completion of the write command,
and therefore no command can be issued for the same bank until precharging is completed.
Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is
also added as a wait interval until precharging is started following the write command. Issuance of
a new command for the same bank is deferred during this interval. The number of Trwl cycles can
be specified by the TRWL bits in MCR.
Rev. 5.0, 09/03, page 329 of 806
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