D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 550

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Transmitting Serial Data (Asynchronous Mode): Figure 15.8 shows a sample flowchart for
transmitting serial data. The procedure for transmitting serial data is:
1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that
2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if
3. To output a break at the end of serial transmission: Set the port SC data register (SCPDR) and
Rev. 5.0, 09/03, page 502 of 806
Note: Numbers in parentheses refer to steps in the preceding procedure description.
the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear
TDRE to 0.
it reads 1); if so, write data in SCTDR, then clear TDRE to 0.
port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register
(SCSCR). For SCPCR and SCPDR settings, see section 15.2.8, SC Port Control Register
(SCPCR)/SC Port Data Register (SCPDR).
Figure 15.7 Sample Flowchart for SCI Initialization
Clear TE and RE bits in SCSCR to 0
Set CKE1 and CKE0 bits in SCSCR
Set TE and RE bits in SCSCR to 1
and set RIE, TEIE, and MPIE bits
(TE and RE bits are 0)
Select communication
Set value in SCBRR
format in SCSMR
interval elapsed?
Initialization
Has a 1-bit
End
Yes
Wait
No
(1)
(2)
(3)
(4)