D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 360

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

all asserted and addresses multiplexed. Control of RAS3U, RAS3L, CASU, CASL, data timing,
and address multiplexing is set with MCR.
Area 3: Area 3 physical address bits A28–A26 are 011. Address bits A31–A29 are ignored and
the address range is H'0C000000 + H'20000000 n – H'0FFFFFFF + H'20000000
and n
Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected
to this space. Byte, word or longword can be selected as the bus width using bits A3SZ1 and
A3SZ0 bits in BCR2 for ordinary memory.
When area 3 space is accessed, CS3 is asserted.
When ordinary memories are connected, the RD signal that can be used as OE and the WE0–WE3
signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait
cycles using the A3W1 and A3W0 bits in WCR2.
When synchronous DRAM is connected, the RAS3U and RAS3L signals, CASU and CASL
signals, RD/WR signal, and byte control signals DQMHH, DQMHL, DQMLH, and DQMLL are
all asserted and addresses multiplexed. The RAS3U and RAS3L signals, CASHH signal, CASHL
signal, CASLH signal, CASLL signal, and RD/WR signal are all asserted and addresses
multiplexed.
Area 4: Area 4 physical address bits A28–A26 are 100. Address bits A31–A29 are ignored and
the address range is H'10000000 + H'20000000
and n
Only ordinary memories such as SRAM and ROM can be connected to this space. Byte, word, or
longword can be selected as the bus width using bits A4SZ1 and A4SZ0 in BCR2. When the area
4 space is accessed, the CS4 signal is asserted. The RD signal that can be used as OE and the
WE0–WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A4W2–A4W0 bits in WCR2.
The number of bus cycles is selected between 0 and 10 wait cycles using bits A4W2 to A4W0 in
WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by means of the
external wait pin (WAIT).
Area 5: Area 5 physical address bits A28–A26 are 101. Address bits A31–A29 are ignored and
the address range is the 64 Mbytes at H'14000000 + H'20000000 n – H'17FFFFFF +
H'20000000
Ordinary memories such as SRAM and ROM as well as burst ROM and PCMCIA interfaces can
be connected to this space. When the PCMCIA interface is used, the IC memory card interface
address range comprises the 32 Mbytes at H'14000000 + H'20000000
H'20000000
Rev. 5.0, 09/03, page 312 of 806
1–6 are the shadow spaces).
1–6 are the shadow spaces).
n (n
n (n = 0–6 and n = 1–6 are the shadow spaces), and the I/O card interface address
0–6 and n
1–6 are the shadow spaces).
n – H'13FFFFFF + H'20000000
n to H'15FFFFFF +
n (n
n (n
0–6
0–6